Memory systems
Memory hierarchy
The memory hierarchy refers to the relative speed and cost per size of different memory technologies. Registers are the fastest memory as the are the closest to the CPU, but they are not suitable for mass storage. Cache is slower than registers but still close to the CPU and fast, but too expensive for mass storage. RAM is ideal for volatile storage of quite a lot of data needed by the CPU and isn't too expensive. Hard disks are slower to access but much cheaper for large amounts of storage.
Locality
Temporal locality - If a memory location is referenced it's likely the same location will be referenced again soon.
Spatial locality - If a memory location is referenced it's likely nearby memory locations will be accessed in the future. It has been shown that 90% of memory accesses are within 2 kilobytes of the previous PC position.
It's therefore a good idea to store data which is accessed frequently in memory as close to the CPU as possible and less frequently accessed data in slower, cheaper storage.
Cache memory
Cache memory is a small amount of memory between the RAM and CPU.
Cache hit and miss
It is much faster for the CPU to retrieve data from the cache than from RAM. If the data the CPU is looking for is in the cache then that is a cache hit and this is good as the data can be retrieved quickly. When the CPU needs data and it isn't in the cache that is a cache miss. The hit rate of the cache is given by the number of cache retrievals over the total number of retrievals.
There are several type of cache miss.
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Compulsory - Misses that would occur regardless of cache size
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Capacity - Misses that occur because the cache is not large enough
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Conflict - Misses that occur due to inefficient cache organisation
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Coherency - Misses that occur due to cache flushes in multiprocessor systems
Multilevel cache
Cache is often split into several levels between the CPU and RAM. Level 1 (L1) cache is the closest and therefore fastest but also smallest, then L2 cache which is slightly slower but larger and L3 cache, further but larger.
Memory organisation
Semiconductor memory
Semiconductor memory is the most common form of main store, more commonly known as RAM. There are two types, static RAM and dynamic RAM. SRAM uses a flip-flop for each bit whereas DRAM uses capacitors. Both types are volatile. DRAM capacitors can leak charge so they need refreshing which incurs a one-off overhead but DRAM has larger capacity and is cheaper to produce so is often used for main memory. SRAM is faster but more expensive and is often used for cache.
Memory organisation
The basic memory element is a memory cell. It has two states, 0 or 1 and is capable of being written or read.
It is important to organise memory efficiently to reduce space and access time. Memory is accessed by row and column and it's important to choose the row/column sizes to reduce the number of addressing components.
Error correction
Errors can occur in a system or between systems. Noise is unwanted information which can lead to errors. It is caused by the physical properties of devices, such as heat and alignment of magnetic fields.
Parity bits
Errors can be detected through the use of a parity bit. This can be used to check if a message has been altered between the sender and receiver. There are two types of parity system - even and odd. In both systems the parity bit is set such that the total number of logical 1s is made to be either even or odd. If the message is invalid then the receiver can request retransmission.
Checksums
Parity bits are vulnerable to burst errors, where an error occurs for a short amount of time and all data sent will be erroneous. Instead, a checksum can be used which is computed from all of the data sent. Then if there is a burst error which affects a lot of the data it is still detected.
Error correcting codes
Error correcting codes use parity bit with checksums for even better error detection. They also allow for single error correction because the result from one check can be used to correct the errors in another.